Public Key Infrastructure and its Applications (PKIA 2026)

Shri Dilip Kumar Barman is presently serving as Deputy Controller (Investigation) in the Office of the Controller of Certifying Authorities, Ministry of Electronics and Information Technology, Government of India. He has over two decades of experience in the field of information technology, digital security, and advanced computer networks. He has played a key role in the design and implementation of national-level initiatives such as UGC NET, ICAR NET, AICTE NET, and the National Medical College Network. His contributions also include spearheading projects for the development of an Indian Browser and Indian SSL Root setups, aimed at strengthening the country's internet resilience and digital sovereignty. His research interests include advanced computer networks, cybersecurity, public key infrastructure, and digital trust services.

Dr. S. D. Sudarsan is the Executive Director at C-DAC Bangalore since August 2020. He has more than three decades of R&D experience as Researcher and Manager in various domains of ICT. Prior to the current assignment, he served as R&D Manager at ABB, Visiting Scientist at US Food & Drug Administration (FDA), USA, Group Head at the Central Research Laboratory (CRL) of Bharat Electronics Limited (BEL), Scientist at funded R&D institutions. He is an alumnus of BITS, Pilani and University of Arkansas at Little Rock, USA for Masters and PhD respectively. He is actively involved with professional bodies including IEEE, ACM, and IETE. He has contributed to various standard related activities at IEC/ISO/BIS and has served in various committees as well as task forces. He has multiple patents, and research publications in peer-reviewed International Journals and Conferences. His areas of specialization include Wireless Communications, Next Generation Networks, Quantum Computing, Cyber Physical Systems, Cyber Security, Industrial IoT, R&D Management, IPR. He leads the domains including Safety and Mission Critical Systems; Quantum Computing, Cyber Security, IoE, HPC etc. Dr. Sudarsan is an outstanding professional, great mentor, industrious and an altruist.

Prof. R. K. Shyamasundar is a Life Fellow of IEEE a Fellow of ACM, Distinguished ACM Speaker, a Distinguished Alumnus of Indian Institute of Science, served as IEEE Distinguished Speaker, and was the founding Dean of School of Technology and Computer Science at the Tata Institute of Fundamental Research. He has been JC Bose National Fellow at TIFR and IIT Bombay and he is an INAE (Indian National Academy of Engineering) Distinguished Professor at the Department of Computer Science, IIT Bombay. He is an Adjunct Professor, NITIE, Mumbai.

Dr. Prasant Misra is a TCS Distinguished Senior Scientist in the Data and Decision Sciences division of TCS Research. He also serves as Visiting Faculty in the Department of Cyber Physical Systems at the Indian Institute of Science, Bangalore. His work broadly lies at the intersection of mobility, energy, and intelligent systems. His current research is centered around modeling, optimization and decision intelligence for operations management of urban mobility and infrastructure systems. He has authored several patents, publications, position papers, and editorials spanning CPS/IoT, mobile and network embedded systems, and electric mobility. He has been recognized by numerous awards and honors, including multiple Best Paper & Poster awards. Notable among them include: the TCS Distinguished Scientist in 2026; the IEEE Computer Society Distinguished Contributor in 2025; the MIT Technology Review TR35 India "Top 10 Innovators Under 35" and the TCS Exemplary Contribution Award in 2017; the ERCIM Alain Bensoussan & EU Marie Curie Fellowship in 2012; and the Australian Government's AusAID Australian Leadership Awards Scholarship in 2008. Dr. Misra actively contributes to the broader scientific and professional community through his involvement with a wide range of academic, industry, and government bodies. He has served on the committees of leading professional organizations (viz. IEEE | ACM | COMSNETS Association); government agencies (viz. MeitY); standard development organizations (viz. BIS | ISO/IEC); editorial boards (viz. Elsevier Ad Hoc Networks Journal | IEEE ITS Magazine | IEEE Communication Magazine). He also plays an active advisory role in public technology policy and capacity-building initiatives. He has over 19 years of professional experience. He received his Ph.D. in Computer Science and Engineering from the University of New South Wales (UNSW), Sydney, and completed his Post-doctoral fellowship from RISE SICS Stockholm (formerly the Swedish Institute of Computer Science). He has held research positions at CSIRO Australia and IISc Bangalore; short-term visiting positions at NICTA Australia, TIFR Mumbai, Universiteit Gent, ETH Zurich; and software engineering positions at NTT DATA. He is a senior member of IEEE and ACM. He is an ACM Distinguished Speaker. He currently serves as the 2026 Chair of IEEE Bangalore Section (the State of Karnataka).

Dr. Abhishek Appaji, a passionate educator and researcher, currently serving as Professor at B.M.S. College of Engineering, Bengaluru. He is also serving as Guest faculty at Maastricht University, the Netherlands. He is a graduate of the Massachusetts Institute of Technology Global Entrepreneurship Bootcamp specializing in new ventures leadership. He obtained his Bachelor of Engineering in Medical Electronics with University Rank from BMSCE, Masters of Technology in Information Technology, and a Masters of Engineering (M.E) in Bioinformatics from University Visvesvaraya College of Engineering, Bengaluru. His Ph.D. was in Mental Health and Neurosciences from Maastricht University, the Netherlands which received the best thesis award and his postdoctoral fellowship from Ohio State University, USA. Abhishek is a Senior Member of IEEE. He has served in various volunteering positions at IEEE. Currently, he is the Treasurer of the IEEE Education Society, and Chair, IEEE Computer Society Bangalore Chapter. He is also in MGA, EAB and Global Conference committees of IEEE. Abhishek has received various grants from Indian agencies like DST, DBT, BIRAC, and from abroad. Abhishek has also worked as a research associate at the Centre for Nanoscience and Engineering (CeNSE), Indian Institute of Science (IISc), Bengaluru. He has a patent granted in Medtech Space. He has more than 100 International/National journal publications and conferences to his credit. He has been a part of more than 200+ Invited expert talks at various conferences, forums, and events. He has renowned laurels including IEEE International Best Paper Award in Malaysia, MGH CamTech Jugadathon Awards, Best Nodal Coordinator award, Gandhian Young Technological Innovation Award 2016 at Rastrapathy Bhavan (President of India House) New Delhi, Elderly care Hackathon (the Netherlands), Winner of Class 5 Massachusetts Institute of Technology (MIT) Global Entrepreneurship Bootcamp, IEEE MGA Young Professional Achievement Award, R10 YP achievement award, DST Inspire Award, IEEE CS Chief of Disruption Award, IEEE SPS Bangalore Outstanding Award, IUCEE TLC Award, IEEE MGA Achievement Award, etc. Recently he was awarded with Theodore W Hissey Young Professionals Award from IEEE Board of Directors. His research interest includes Neuroscience, AI, Deep Learning and Entrepreneurship.

Prof. Debabrata Das is serving as Director of IIIT-Bangalore (IIIT-B). Before joining IIIT-B in 2002, he had served at G S Sanyal School of Telecommunication at IIT Kharagpur and later at Kirana Networks in New Jersey, USA. He is Project Officer of National Mission for Interdisciplinary Cyber Physical Systems in the areas of Advanced Communication System, from DST, Govt of India. He was PI of multiple sponsored projects from Intel, Hewlett Packard, Microsoft, Motorola Research, Tejas Networks, Nokia, Govt. of India, in the areas of Broadband Wireless MAC/QoS/Energy-saving, and IMS. His main areas of research interest are IoT and Wireless Access Network's MAC, QoS, Power saving. Dr. Das received his Ph.D. degree from the Indian Institute of Technology Kharagpur. He has more than 220 peer reviewed papers in different Transaction/Journals and International Conferences. Dr. Das has received 9 best paper awards. He has 12 US/Indian patents and 10 more are under review. He and his wireless network team had contributed ideas to IEEE Wireless Broadband Standard. He has received Prof. K. Sreenivasan Memorial Award 2017 for excellent teaching and Prof. S V C Aiya Memorial Award 2022 for Research in the areas of Telecommunication and Electronics from IETE. Dr. Das is recipient of IEEE Region-10 Outstanding Volunteer Award 2020, Global IEEE MGA Achievement Award 2012 and Outstanding Volunteer Award IEEE Bangalore Section 2008. He is Fellow-IETE, Fellow-IE and SM-IEEE. He is a Member of National Academy of Science India (NASI). He was Chairman of IEEE India Council for the year 2023 and 2024. He was Chairman of IEEE Bangalore Section 2017. Dr. Das is in Steering, Empower and Technical committees of multiple Departments of Government of India and Government of Karnataka.

Shri Magesh Ethirajan has taken charge as Director General, C-DAC since April 2022. He is spearheading the National Mission Programs like the National Supercomputing Mission, Digital India RISC-V (DIR-V) and C-DAC Mission Mode Programs in HPC, AI, Cyber Security, Quantum Computing and Next Generation Computing. Since June 2023, he is also assigned with the Additional Charge as Director General, Centre for Materials for Electronics Technology (C-MET). Under his leadership, C-MET is continuing to develop leapfrogging electronic materials technologies such as Compound semiconductors for high power devices, ultra high purity materials for National Semiconductor Mission, Quantum & 2D materials, resource efficiency and circular economy through e-waste recycling, niche ceramic and composite materials for 5G & 6G communications etc. Prior to this Shri Magesh was heading C-DAC Thiruvananthapuram Centre as Executive Director, C-DAC Hyderabad Centre as Director and has also served as Vice President of MNC. Shri Magesh has more than 29 years of diversified experience ranging from Design Engineering, Project Management and delivery of turnkey projects. He has in depth expertise in Electronics and CHIP design, VLSI, Hardware, IP, Complete Product Cycle. He was also responsible for SOC integration, front end to backend, tape-out and silicon validation, interfacing with various functional groups to deliver tested products and managed various ASIC tape-out for customers. Leveraging three decades of his technology expertise, Shri Magesh has significantly contributed towards end-to-end mission planning of national importance, design, integration and analysis. His innovative contributions, particularly the strategies adopted in R&D towards realising 25 Plus ASIC/CHIP, C-DAC's indigenous series 32/64 bit RISCV based of Processor called VEGA, and SOC's called THEJAS under National Microprocessor Development Program, development of 20 Petaflops Supercomputing Facility with indigenous 'RUDRA Server Board', TRINETRA High Speed Interconnect, designing and making our own 'RISC-V based Chip' and 96 core ARM 64bit Processor in 5 nano meter for India first HPC SOC towards Exa-scale computing to 'HPC Storage' to 'HPC-AI Converged Solutions for high level projects of national importance like Safe City including ERSS and Smart Cities, Integrated Cyber Physical Systems, AI based Anomaly Detection for Cyber Security, establishing first of its kind AI Specific National Critical Cloud Infrastructure, HPC-AI Converged Processor has put a good foundation for launch of various indigenous products and solutions making our country self-reliant and in line with the goals of AatmaNirbhar Bharat and Digital India. His visionary approach in conceptualizing ideas in Quantum Technologies is helping to establish a Quantum Computer. This shall enable develop applications to solve grand challenges and societal problems having economic impact leveraging cutting edge scientific research for India's sustainable development.

Dr. Sanjay Bahl is currently Controller of Certifying Authorities and Director General, CERT-In. He has been providing consultancy in the areas of governance, risk, compliance, security, privacy, forensics, investigation and fraud management to national level projects in India. Prior to CERT-In, he was the chief security officer for Microsoft Corporation in India where he was responsible for interaction with the government, academia, key strategic accounts and the CXO community with respect to Microsoft's security policy. Prior to joining Microsoft, Dr. Bahl was the global CSO of TCS where he established an enterprise-wide converged security environment and effectively addressed risk management and security across the organization worldwide. He has also worked with academic and professional communities as well as government groups to enhance their awareness of comprehensive security models. He has been in the IT industry since 1984 with experience in various areas.Dr. Bahl is and has been a member of various security committees at national and international level.

Dr. Balaji Rajendran is a Scientist 'F' and heads the Resilient Information Systems and Engineering (RISE) Group at C-DAC Bangalore. With over 24 years of pioneering R&D experience, he has been instrumental in shaping digital trust and cybersecurity ecosystem through national initiatives, international collaborations, and indigenous technology development. He has played a pivotal role in proliferating Digital Signatures across the country through lectures, capacity building, and interactive content development. He established Asia's first Centre of Excellence in DNS Security with support from the government and industry and continues to drive mission-critical programs that strengthen the nation's cyber resilience. He is leading the National Centre for Digital Trust (NCDT), a pioneering initiative aimed at creating the next generation of digital trust frameworks and technologies for the systems and services that surround our everyday lives.

Jean Everson Martina is a Professor of Computer Science at the Federal University of Santa Catarina, Brazil, and a researcher at the Computer Security Laboratory, LabSEC. His work focuses on applied cryptography, digital trust infrastructures, public key infrastructure, electronic signatures, digital identity, verifiable credentials, blockchain, long-term validation, and post-quantum cryptography. He has contributed to several Brazilian national initiatives involving digital signatures, digital documents, trust services, and government digital infrastructures, working in cooperation with public institutions and industry. He also participates in international cooperation and standardization activities related to digital trust and cross-border interoperability.

Prof. Ashutosh Saxena (PhD 1997 in AI from DAVV title: Utility of Genetic Algorithm and Neural Network for Cell Placement-A Special Case for VLSI Standard Cell Placement) is an industry expert and academician with over two decades of experience, 100+ international publications with Scopus h-index of 17, along with 31 filled patents out of which 27 are now US granted patents. Authored two books, one on “PKI: Concept, Design and Deployment” (Tata McGraw Hill Publications 2004) and second on “Blockchain Technology: Concepts and Applications”, (Wiley Publications 2020). He also had a credit to adapt one book titled “Information Security: Principles and Practice, An Indian Adaptation by Mark Stamp; (Wiley Publications 2023). His research interest is in the areas of information security and privacy. Worked as Associate Professor at the IDRBT (established by Reserve Bank of India), Hyderabad, (1998-2006) on many national level projects. Joined Infosys (2006-16) and worked as Principal Research Scientist & Associate Vice President, at Infosys Labs, Hyderabad where he led security research as part of the Security Center of Excellence, Infosys Center for Advanced Technologies, conceived security solutions that have already been deployed to many clients. He has been a member of the review board for many international journals, conferences and committees. He also served as Adjunct Faculty at NIT Warangal for one year, worked as Professor (CS) at CRRAO-AIMSCS, University of Hyderabad Campus, Hyderabad, and now as Prof and Dean CMR Technical Campus, Hyderabad.

As digital transformation accelerates, individual technologies are hitting structural boundaries: Artificial Intelligence faces data privacy and monopolisation crises, while Blockchain seeks scalable, real-world utility beyond speculation. This talk tries to explore the cutting-edge convergence of these two paradigm-shifting technologies and their combined impact on legacy industries. We will examine how decentralized architecture provides an immutable layer of truth for AI models—ensuring data provenance, securing decentralized infrastructure, and enabling autonomous AI agents to conduct secure economic transactions via smart contracts. Attendees will discover how this technical synergy is creating privacy-preserving diagnostic tools in healthcare, streamlining autonomous supply chain logistics, and democratising real estate through algorithmic tokenization.

Dr. Debapriya Basu Roy received his PhD degree from IIT Kharagpur and was a post-doctoral fellow with the Technical University of Munich. He is currently an Assistant Professor with the Department of Computer Science and Engineering, Indian Institute of Technology Kanpur. His research interests include applied cryptography, hardware security, post-quantum cryptography, side channel analysis and digital VLSI. Some of his notable contributions in the domain of hardware security are efficient implementation of elliptic curve cryptography, side-channel leakage quantification and implementation of post-quantum cryptography on FPGAs.

Sikhar Patranabis is a cryptographer and a staff research scientist at IBM Research India. He is a member of the Foundational Cryptography group within IBM Research. His research interests are in theoretical and applied cryptography, with a recent focus on quantum-safe cryptography and succinctly verifiable, privacy-enhancing cryptographic techniques. Prior to joining IBM, he was a staff researcher at VISA Research USA and a postdoctoral researcher at ETH Zurich, Switzerland. He received his B.Tech and PhD from IIT Kharagpur. His research has appeared at reputed crypto/security venues, such as the Journal of Cryptology (JoC), Crypto, Eurocrypt, Asiacrypt, IEEE S&P, ACM CCS, USENIX Security, NDSS, etc. He is a young associate of the Indian Academy of Sciences (IASc) and the Indian National Academy of Engineering (INAE). His research has been recognized by an IACR best early-career paper award at ASIACRYPT 2022, an IBM PhD fellowship, and a Qualcomm Research Innovation Fellowship. He has served on multiple program committees and editorial boards of top conferences and journals in crypto/security. He is also actively involved in various outreach activities organized by ACM India.

Isogenies have emerged as a viable alternative to lattices for post-quantum cryptography over the past 20 years. However, due to the uniquely complex underlying mathematical features and security/efficiency properties, the landscape of isogeny-based cryptography has remained somewhat limited and inaccessible to the wider cryptographic community. Additionally, building new cryptographic applications from isogenies has been a potentially tedious and time-consuming task. In this talk, he will present an overview of two frameworks for isogeny-based cryptography, namely “cryptographic group actions” and “cryptographic forensic categories”. These frameworks enable viewing isogeny-based cryptography through the lens of abstract and easy-to-understand algebraic structures combined with simple cryptographic hardness assumptions. He will showcase some applications of these frameworks in: (i) enabling simplified expositions of well-known cryptographic constructions from isogenies (e.g., CSIDH-based public-key encryption and the SQIsign family of digital signatures), and (ii) realizing new (plausibly) post-quantum instances of advanced cryptographic primitives from isogenies. He hope to demonstrate the simplicity and usability of these frameworks for isogeny non-experts. Along the way, He will also talk about some hard problems that form the basis of isogeny-based cryptography, and their classical/quantum hardness as of today. No prior background in either cryptography or quantum computing will be necessary to follow the talk.

As the Executive Director and Chief Executive Officer, Rao Munukutla is responsible for developing the Airport City for BIAL, whose majority shareholder (74%) is the Fairfax Group, Canada. Bengaluru Airport City is being developed to standards that will be unprecedented, a futuristic city where Innovation happens 24/7 and that will be a test bed for 'Global Urban Solutions'. It is planned as Sustainable, Smart & Vibrant city celebrating a culture of innovation. In a career spanning over three decades, Rao has handled leadership roles in the infrastructure space and delivered various multi-billion-dollar projects in Singapore, Indonesia, Malaysia, India, Australia and Myanmar. These include massive Bintan Beach International Resort Project in Indonesia, a G-to-G collaboration between Indonesia and Singapore. During his previous stint in India, Rao led the operations of Jurong International as CEO of JTCi India, a wholly owned subsidiary of JTC Corp Singapore. Rao is a recipient of the National Science & Technology Board (NSTB) Gold Medal in Singapore.

Mr. William O. Ferguson is an IEEE Senior Member and a member of the IEEE Computer Society, the IEEE Standards Association, and the IEEE Aerospace and Electronic Systems Society. Since 2023 he has served as Technical Editor of IEEE P3536 within the Space Systems Cybersecurity Working Group of the IEEE Standards Association, coordinating contributions from government, industry, and academic stakeholders across four continents and carrying the draft from scoping through ballot. Since 2026 he has also led the working group's Space Systems Integration Subgroup, which specifies security requirements for the interfaces where ground control systems, RF and optical links, spacecraft, user terminals, and third party services interconnect, and establishes the validation methodology for multi segment security architectures. He is currently developing the IEEE Space Systems Resilience Engineering pilot cohort, an IEEE SA training initiative that translates P3536 into taught practice for working engineers and moves practicing cybersecurity professionals into space capable roles. He is an author on three peer reviewed IEEE works on space system security, published in the IEEE Journal of Radio Frequency Identification (2025), the IEEE International Conference on Wireless for Space and Extreme Environments (2024), and the IEEE International Conference on Space Mission Challenges for Information Technology (2024).

Most space missions still add security after the design is fixed, or import rigid security baselines that do not fit the mission. IEEE P3536, under development within the IEEE Standards Association, takes a different route. By focusing on failure modes, which are universally understood and prioritized in the space system engineering community, it enables each mission to derive contextualized, mission specific technical security requirements, and it applies existing space system design artifacts as prerequisites so those requirements stay aligned with the actual design. The process has two prerequisites and six steps. The prerequisites map space mission objectives to failure modes of interest, and failure modes of interest to existing design reference artifacts. The six steps then formally document technical system boundaries, attack surfaces, threat techniques, protection techniques, the technical traceability between them, and finally the secure blocks: the functional technical requirements, with traceability, reviewed as part of the system engineering process. This talk, from the standard's Technical Editor and lead of its Space Systems Integration Subgroup, walks through that process end to end and shows how it produces traceable security requirements for segments, subsystems, and components rather than a generic checklist. It gives particular attention to the integration layer, where ground control systems, RF and optical links, spacecraft, user terminals, and third party services interconnect and where adversaries exploit trust between segments to move laterally. It also explains how the process serves sovereign export control and classification regimes as well as rapid or budget constrained New Space and open science missions, without a single global baseline.